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1 of 20 note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneousl y available through various sales channels. for information about device errata, click here: www.maxim - ic.com/errata . general description the ds1500 is a full - function, year 2000 - compliant real - time clock/calendar (rtc) with an alarm, watchdog timer, power - on reset, battery monitors, 256 bytes of on - board nonvolatile (nv) sram, nv control for backing u p an external sram, and a 32.768khz output. user access to all registers within the ds1500 is accomplished with a byte - wide interface, as shown in figure 7 . the rtc registers contain century, year, month, date, day, hours, minutes, and seconds data in 24 - hour binary - coded decimal (bcd) format. corrections for day of month and leap year are made automatically. applications remote systems battery - backed systems telecom switches office equipment consumer electronics pin configuratio n and typical operating circuit appear at end of data sheet. features ? bcd- coded century, year, month, date, day, hours, minutes, and seconds with automatic leap - year compensation valid up to the year 2100 ? programmable watchdog timer and rtc alarm ? century register; y2k - compliant rtc ? automatic battery backup and write protection to external sram ? +5v or +3.3v operation ? precision power - on reset ? power - control circuitry supports system power - on from date/day/time alarm or key closure ? 256 bytes user nv ram ? auxil iary battery input ? accuracy better than 1 minute/month at +25c ? day-of - week/date alarm register ? battery voltage - level indicator flags ? optional industrial temperature range: - 40c to +85c ordering information part temp range voltage (v) pin - package 0b top mark* ds1500we+ 0 c to +70 c 3.3 32 tsop ds1500w ds1500wen+ - 40c to +85c 3.3 32 tsop ds1500wn ds1500ye+ 0 c to +70 c 5 .0 32 tsop ds1500y ds1500yen+ - 40c to +85c 5.0 32 tsop ds1500yn + denotes a lead (pb) - free/rohs - compliant device. * a + anywhere on the top mark indicates a le ad (pb) - free/rohs - compliant device. an n indicates an industrial temperature range device. ds1500 y2k watchdog rtc with nonvolatile control 19 - 6 130 ; rev 11 /11
ds1500 y2kc watchdog rtc with nonvolatile control 2 of 20 absolute maximum rat ings voltage range on any pin relative to ground.. - 0.5v to +6.0v operating temperature range (industrial) ... - 40c to +85c (note 1) operating temperature range (commercial) . ... - 0c to + 70 c storage temperature range . - 55c to +125c lead temperature (soldering, 10s ). . + 300c solderin g temperature (reflow) . +260c stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to the absolute maximum rating co nditions for extended periods may affect device reliability. recommended dc opera ting conditions (t a = over the operating range. ) parameter symbol conditions min typ max units power supply voltage (note 2) v cc 5v (y) 4.5 5.0 5.5 v 3.3v (w) 3.0 3.3 3.6 logic 1 voltage all inputs (note 2) v ih y 2.2 v cc + 0.3 v w 2.0 v cc + 0.3 pullup voltage, irq , pwr , and rst outputs v pu (note 2) 5.5 v logic 0 voltage all inputs (note 2) v il y - 0.3 +0.8 v w - 0.3 +0.6 battery voltage (n ote 2) v bat 2.5 3.0 3.7 v auxiliary battery voltage (note 2) v baux y 2.5 3.0 5.3 v w 2.5 3.0 3.7 dc electrical charac teristics (v ccmin < v cci < v ccmax , t a = over the operating range.) parameter symbol conditions min typ max units a ctive supply current (note 3) i cc y 15 ma w 10 ttl standby current (cs = v ih ) i cc1 y 5 ma w 4 cmos standby current (cs v cci - 0.2v) i cc2 y 5 ma w 4 input leakage current (any input) i il -1 +1 a output leakage current (any output) i ol - 1 +1 a output logic 1 voltage (i out = - 1.0ma) v oh (note 2) 2.4 v output logic 0 voltage (i out = 2.1ma, dq0 C 7, ceo i out = 5.0ma, irq , i out = 7.0ma pwr , and rst ) v ol1 (note 2) 0.4 v v ol2 (notes 2, 4) 0.4 v battery low, flag trip point (note 2) v blf y 2.0 v w 1.9 output voltage (i cco1 = 85ma ) (note 5) v cco1 y v cci - 0.3 v w power - fail voltage (note 2) v pf y 4.20 4.50 v w 2.75 2.97 battery switchover voltage v so (notes 2, 6) v bat, v baux, or v pf v
ds1500 y2kc watchdog rtc with nonvolatile control 3 of 20 parameter symbol conditions min typ max units outpu t voltage (i cco2 = 50a) v cco2 (note 7) v bat - 0.3 v battery leakage current i lkg 10 100 na dc electrical charac teristics (v cc = 0v, t a = over the operating range.) parameter symbol conditions min typ max units battery current, bb3 2 = 0, eosc = 0 i bat1 (notes 8, 9) 0.27 1.0 a battery current, bb32 = 0, eosc = 1 i bat2 (notes 8, 9) 0.01 0.1 a v baux current bb32 = 1, sqw open i baux (notes 8, 9) 2 a crystal specificatio ns parameter symbol conditions min typ max units nomina l frequency f o 32.768 khz series resistance esr 45 k ? load capacitance c l 6 pf note: the crystal, traces, and crystal input pins should be isolated from rf generating signals. refer to application note 58: crystal considerations for ma xim real - time clocks (rtcs) for additional specifications. ac operating charact eristics (v cci = 5.0v 10% , t a = over the operating range.) parameter symbol conditions min typ max units read cycle time t rc 70 ns address access time t aa 70 ns cs to dq low - z t csl (note 10) 5 ns cs access time t csa 70 ns cs data off time t csz (note 10) 25 ns oe to dq low - z (0c to +85c) t oel (note 10) 5 ns oe to dq low - z ( - 40c to 0c) t oel (note 10) 2 ns oe access time t oea 35 ns oe data off time t oez (note 10) 25 ns output hold from address t oh 5 ns write cycle time t wc 70 ns address setup time t as 0 ns we pulse width t wew 50 ns cs pulse width t csw 55 ns data setup time t ds 30 ns data hold time t dh 5 ns address hold time t ah 0 ns we data off time t wez (note 10) 25 ns write recovery time t wr 15 ns cei to ceo propagation delay t cepd 10 ns pulse width, oe , we , or cs high pw high 20 ns pulse width, oe , we , or cs low pw low 70 ns
ds1500 y2kc watchdog rtc with nonvolatile control 4 of 20 ac o perating characteris tics (continued) (v cci = 3.3v 10% , t a = over the operating range.) parameter symbol conditions min typ max units read cycle time t rc 120 ns address access time t aa 120 ns cs to dq low - z t csl (note 10) 5 ns c s access time t csa 120 ns cs data off time t csz (note 10) 40 ns oe to dq low - z (0c to +85c) t oel (note 10) 5 ns oe to dq low - z ( - 40c to 0c) t oel (note 10) 2 ns oe access time t oea 100 ns oe data off time t oez (note 10) 35 ns output hold from address t oh 5 ns write cycle time t wc 120 ns address setup time t as 0 ns we pulse width t wew 100 ns cs pulse width t csw 110 ns data setup time t ds 80 ns data hold time t dh 5 ns address hold time t ah 0 ns we data o ff time t wez (note 10) 40 ns write recovery time t wr 15 ns cei to ceo propagation delay t cepd 10 ns pulse width, oe , we , or cs high pw high 40 ns pulse width, oe , we , or cs low pw low 100 ns figure 1 . read cycle timing t rc t csa t oea t csl t oel t oh t oez t aa valid dq0-dq7 oe cs a0-a4 t csz
ds1500 y2kc watchdog rtc with nonvolatile control 5 of 20 figure 2 . write cycle timing, write - enable - controlled figure 3 . write cycle timing, chip - select - controlled t wc t ah t ds t as t wez t dh t wr t as data input dq0-dq7 we cs a0-a4 data output data input t wew valid valid t wc t ah t ds t as t dh t wr t as data input dq0-dq7 we cs a0-a4 data input t csw valid valid
ds1500 y2kc watchdog rtc with nonvolatile control 6 of 20 figure 4 . burst mode timing waveform a0 C a4 dq0 C dq7 oe , we , or cs 13h pw high pw low power- up/down characterist ics ( figure 5 ) parameter symbol conditions min typ max units cs , cei , or we at v ih before power - fail t pf 0 s v cci fall time: v pf(max) to v pf(min) t f 300 s v cci fall time: v pf(min) to v so t fb 10 s v cci rise time: v pf(min) to v pf(max) t r 0 s v pf to rst high t rec 35 200 ms capacitance (t a = +25c) parameter symbol min typ max units capacitance on all input pins c in 10 pf capacitance on irq , pwr , rst , and dq pins c io 10 pf ac test conditions output load input pulse levels timing measurement reference levels input pulse rise and fall times (y) 50pf + 1ttl gate 0v to 3.0v for 5v operation input: 1.5v 5ns (w) 25pf + 1 ttl gate output: 1.5v
ds1500 y2kc watchdog rtc with nonvolatile control 7 of 20 figure 5 . 5v power - up/down waveform timing outputs v cci v pf(max) v pf(min) inputs high - z rst don't care valid recognized recognized valid t f t fb t pf t dr v so t r t rec warning: under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery - backup mode.
ds1500 y2kc watchdog rtc with nonvolatile control 8 of 20 wakeup/kickstart tim ing (t a = +25c) ( figure 6 ) parameter symbol conditions min typ max units kickstart - input pulse width t kspw 2 s wakeup/kickstart power - on timeout t poto (note 11) 2 s note: time intervals shown above are referenced in wakeup/kickstart. figure 6 . wakeup/kickstart timing diagram note 1: limits at - 40c are not production tested and are guaranteed by design. note 2: voltage referenced to ground. note 3: outputs are open. note 4: the irq , pwr , and rst outputs are open drain. note 5: value for voltage and currents is from the v cci input pin to the v cco pin. note 6: if v pf is less than v bat and v baux , the device power is switched from v cc to the greater of v bat or v b aux when v cc drops below v pf . if v pf is greater than v bat and v b aux , the device power is switched from v cc to the greater of v bat or v b aux when v cc drops below the greater of v bat or v b aux . note 7: value for voltage and currents is from the v bat or v b aux input pin to the v cco pin . note 8: i bat1 and i bat2 are specified with v cco unconnected and do not include any ram current. note 9: v bat or v b aux current. using a 32 . 768 k hz crystal connected to x1 and x2. note 10: these parameters are sampled with a 5pf load and are not 1 00% tested. note 11: typical values are at +25c, nominal (active) supply, unless otherwise noted. note 12: if the oscillator is not enabled, the startup time of the oscillator after v cci is applied is added to the wakeup/kickstart timeout.
ds1500 y2kc watchdog rtc with nonvolatile control 9 of 20 pin description pin name function 1 sqw square - wave output. when enabled, the sqw pin outputs a 32.768khz square wave. if the square wave ( e32k ) and battery - backup 32khz (bb32) bits are enabled, power is provided by v baux when v cc is absent. 2 ks kickstart input. this pin is used to wake up a system from an external event, such as a key closure. the ks pin is normally connected using a pullup resistor to v baux . if the ks function is not used, connect to ground. 3 v bat battery input for any standard 3v lithium cell or other energy source. battery voltage must be held between 2.5v and 3.7v for proper operation. ul recognized to ensure against reverse charging current when used with a lithium battery. if not used, connect to ground.* 4 v baux auxiliary battery input for any standard 3v lithium cell or other energy source. battery voltage must be held between 2.5v and 3.7v for proper operation. provides backup power to the device, and provides power for auxiliary functions. ul recognized to ensure against reverse charging current when used with a lithium battery. if not used, connect to ground.* 5 ceo chip - enable output. buffered chip - enable output signal for external sram switches high when v cci falls below the power - fail point v pf . 6 cei chip - enable input. input for chi p - enable signal for external sram. 7 we write - enable input. active - low input that enables dq0 C dq7 for data input to the device. 8 v cc1 dc power is applied to the device on these pins. v cc is the positive terminal. when power is applied within the normal limits, the device is fully accessible and data can be written and read. when v cc drops below the normal limits, reads and writes are inhibited. as v cc drops below the battery voltage, the ram and timekeeping circuits are switched over to the battery. 9 v cc0 buffered v cc output to external sram. switches to either v bat or v baux when in data retention mode. 10 n.c. no connect ion 11 pwr power - on output (open drain). this output, if used, is normally connected to power - supply control circuitry. this pin req uires a pullup resistor connected to a positive supply to operate correctly. 12, 13 x1, x2 connections for a standard 32.768khz quartz crystal. for greatest accuracy, the ds1500 must be used with a crystal that has a specified load capacitance of either 6 pf or 12.5pf. the crystal select (cs) bit in control register b is used to select operation with a 6pf or 12.5pf crystal. the crystal is attached directly to the x1 and x2 pins. there is no need for external capacitors or resistors. an external 32.768khz o scillator can also drive the ds1500. in this configuration, the x1 pin is connected to the external oscillator signal and the x2 pin is left unconnected . for more information about crystal selection and crystal layout considerations, refer to applic ation note 5 8: crystal considerations with maxim real - time clocks (rtcs) . see figure 8 . 14 rst reset output (open drain). this output, if used, is normally connected to a microprocessor - reset input. this pin requires a pullup resistor connected to a positive supply to operate correctly. when rst is active, the device is not accessible. 15 irq interrupt output (open drain). this output, if used, is normally connected to a microprocessor interrupt input. this pin requires a pullup resistor connected to a positive supply to operate correctly. 16C 20 a4 C a0 address inputs. selects one of 17 register locations. 21 C 23, 25 C 29 dq0 C dq7 data i/o pins for 8 - bit parallel data transfer. 24, 31 gnd dc power is applied t o the device on these pins. v cc is the positive terminal. when power is applied within the normal limits, the device is fully accessible and data can be written and read. when v cc drops below the normal limits, reads and writes are inhibited. as v cc drops below the battery voltage, the ram and timekeeping circuits are switched over to the battery. 30 cs chip - select input. active - low input to enable the device. 32 oe output - enable input. active - low input that enables dq0 C dq7 for data output from the device * see conditions of acceptability at www.maxim - ic.com/techsupport/qa/ntrl.htm .
ds1500 y2kc watchdog rtc with nonvolatile control 10 of 20 figure 7 . block diagram figure 8 . typical crystal layout crystal x1 x2 gnd local ground plane (layer 2) v cco rst pwr ceo 256 x 8 nv sram power control write protection, and power - on reset 16 x 8 clock and control registers v bat v bat v baux gnd ks cei a0 C a4 dq0 C dq7 cs we oe x1 x2 32.768khz clock oscillator irq sqw clock alarm and watchdog countdown maxim ds1500
ds1500 y2kc watchdog rtc with nonvolatile control 11 of 20 detailed description the rtc registers are double buffered into an internal and external set. the user has direct access to the external set. clock/calendar updates to the external set of registers can be disabled and ena bled to allow the user to access static data. when the crystal oscillator is turned on, the internal set of registers are continuously updated; this occurs regardless of external register settings to guarantee that accurate rtc information is always mainta ined. the ds1500 contains its own power - fail circuitry that automatically deselects the device when the v cci supply falls below a power - fail trip point. this feature provides a high degree of data security during unpredictable system operation caused by l ow v cci levels. an external sram can be made nonvolatile by using the v cco and ceo pins. nonvolatile control of the external sram is analogous to that of the rtc registers. when v cci slews down during a power fail, ceo is driven to an inactive level regard less of cei . this write protection occurs when v cci is less than the power - fail trip point. the ds1500 has interrupt ( irq ), power control ( pwr ), and reset ( rst ) outputs that can be used to control cpu activity. the irq interrupt or rst outputs can be invo ked as the result of a time -of - day alarm, cpu watchdog alarm, or a kickstart signal. the ds1500 power - control circuitry allows the system to be powered on by an external stimulus, such as a keyboard or by a time and date (wakeup) alarm. the pwr output pin can be triggered by one or either of these events, and can be used to turn on an external power supply. the pwr pin is under software control, so that when a task is complete, the system power can then be shut down. the ds1500 power - on reset can be used to detect a system power - down or failure and hold the cpu in a safe reset state until normal power returns and stabilizes; the rst output is used for this function. the ds1500 is a clock/calendar chip with the features described above. an external crystal a nd battery are the only components required to maintain time -of - day and memory status in the absence of power. . table 1 . rtc operating modes v cci cs oe we dq0 C dq7 a0 C a4 mode power v cci > v pf v ih x x high - z x deselect standby v il x v il d in a in write active v il v il v ih d out a in read active v il v ih v ih high - z a in read active v so < v cci < v pf x x x high - z x deselect cmos standby v cci < v so < v pf x x x high - z x data retention battery current data read mode the ds1500 is in rea d mode whenever cs (chip select) and oe (output enable) are low and we (write enable) is high. the device architecture allows ripple - through access to any valid address location. valid data is available at the dq pins within t aa (address access) after the last address input is stable, provided that cs and oe access times are satisfied. if cs or oe access times are not met, valid data is available at the latter of chip - enable access (t csa ) or at output - enable access time (t oea ). the state of the data input/o utput pins (dq) is controlled by cs and oe . if the outputs are activated before t aa , the data lines are driven to an intermediate state until t aa . if the address inputs are changed while cs and oe remain valid, output data remains valid for output - data hol d time (t oh ) but then goes indeterminate until the next address access (table 1). data write mode the ds1500 is in write mode whenever cs and we are in their active state. the start of a write is referenced to the latter occurring transition of cs or we. the addresses must be held valid throughout the cycle. cs or we must return inactive for a minimum of t wr prior to the initiation of a subsequent read or write cycle. data in must be valid t ds prior to the end of the write and remain valid for t dh afterwar d. in a typical application, the oe signal is high during a write cycle. however, oe can be active provided that care is taken with the data bus to avoid bus contention. if oe is low prior to a high -to - low transition on we , the data bus can become active w ith read data defined by the address inputs. a low transition on we then disables the outputs t wez after we goes active (table 1).
ds1500 y2kc watchdog rtc with nonvolatile control 12 of 20 data retention mode the ds1500 is fully accessible and data can be written and read only when v cci is greater than v pf . howe ver, when v cci falls below the power - fail point v pf (point at which write protection occurs) the internal clock registers and sram are blocked from any access. while in the data retention mode, all inputs are dont cares and outputs go to a high - z state , w ith the exception of v cco , ceo , and with the possible exception of ks , pwr , sqw, and rst . ceo is forced high. if v pf is less than v bat and v baux , the device power is switched from v cci to the greater of v bat and v baux when v cci drops below v pf . if v pf is g reater than v bat and v baux , the device power and v cco are switched from v cci to the larger of v bat and v baux when v cci drops below the larger of v bat and v baux . rtc operation and sram data are maintained from the battery until v cc is returned to nominal le vels ( table 1). if the square - wave and battery - backup 32khz functions are enabled, v baux always provides power for the square - wave output, when the device is in battery - backup mode. all control, data, and address signals must be no more than 0.3v above v cc i . auxiliary battery the v baux input is provided to supply power from an auxiliary battery for the ds1500 kickstart and square - wave output features in the absence of v cci . this power source must be available to use these auxiliary features when no v cci is applied to the device. this auxiliary battery can be used as the primary backup power source for maintaining the clock/calendar and external sram. this occurs if the v bat pin is at a lower voltage than v baux . if the ds1500 is to be backed - up using a sing le battery with the auxiliary features enabled, then v baux should be used and connected to v bat . if v baux is not to be used, it should be grounded. power- on reset a temperature - compensated comparator circuit monitors the level of v cci . when v cci falls to the power - fail trip point, the rst signal (open drain) is pulled low. when v cci returns to nominal levels, the rst signal continues to be pulled low for a period of t rec . the power - on reset function is independent of the rtc oscillator and therefore operat ional whether or not the oscillator is enabled. time and date operat ion the time and date information is obtained by reading the appropriate register bytes. table 2 shows the rtc registers. the time and date are set or initialized by writing the appropriate register bytes. the contents of the time and date registers are in the binary - coded decimal (bcd) format. hours are in 24- hour mode. the day -of - week register increments at midnight. values that correspond to the day of week are user - defined, but must be sequential (i.e., if 1 equals sunday, then 2 equals monday, and so on). illogical time and date entries result in undefined operation. reading the clock when reading the clock and calendar data, it is possible to access the regis ters while an update (once per second) occurs. there are three ways to avoid using invalid time and date data. the first method uses the transfer enable (te) bit in the control b register. transfers are halted when a 0 is written to the te bit. setting te to 0 halts updates to the user - accessible registers, while allowing the internal registers to advance. after the registers are read, the te bit should be written to 1. te must be kept at 1 for at least 366s to ensure a user register update. the time and date registers can be read and stored in temporary variables. the time and date registers are then read again, and compared to the first values. if the values do not match, the time and da te registers should be read a third time and compared to the previous values. this should be done until two consecutive reads of the time and date registers match. the te bit should always be enabled when using this method for reading the time and date,. the third method of reading the time and date uses the alarm function. the alarm can be configured to activate once per second, and the time -of - day alarm - interrupt enable bit (tie) is enabled. the te bit should always be enabled. when the irq pin goes acti ve, the time and date information does not change until the next update.
ds1500 y2kc watchdog rtc with nonvolatile control 13 of 20 setting the clock it is recommended to halt updates to the external set of double buffered rtc registers when writing to the clock. the (te) bit should be used as described above befo re loading the rtc registers with the desired rtc count (day, date, and time) in 24 - hour bcd format. setting the (te) bit to 1 transfers the new values written to the internal rtc registers and allows normal operation to resume. clock accuracy a standard 32.768khz quartz crystal should be directly connected to the ds1500 x1 and x2 oscillator pins. the crystal selected for use should have a specified load capacitance (c l ) of either 6pf or 12.5pf, and the crystal select (cs) bit set accordingly. for more inf ormation about crystal selection and crystal layout considerations, refer to application note 58: crystal considerations with maxim real- time clocks (rtcs) . an external 32.768khz oscillator can also drive the ds1500. to achieve low - power operation w hen using an external oscillator, it may be necessary to connect the x1 pin to the external oscillator signal through a series connection consisting of a resistor and a capacitor. a typical configuration consists of a 1.0m resistor in series with a 100pf c eramic capacitor. when using an external oscillator the x2 pin must be left open. table 2 . register map address data function bcd range b7 b6 b5 b4 b3 b2 b1 b0 00h 0 1 0 seconds seconds seconds 00 C 59 01h 0 10 minutes minutes minutes 00 C 59 02h 0 0 10 hours hour hours 00 C 23 03h 0 0 0 0 0 day day 1 C 7 04h 0 0 10 date date date 01 C 31 05h eosc e32k bb32 10 mo month month 01 C 12 06h 10 year year year 00 C 9 9 07h 10 century century century 00 C 39 08h am1 10 seconds seconds alarm seconds 00 C 59 09h am2 10 minutes minutes alarm minutes 00 C 59 0ah am3 0 10 hours hour alarm hours 00 C 23 0b h am4 dy/dt 10 date day/date alarm day/date 1 C 7/1 C 31 0c h 0. 1 second 0.01 second watchdog 00 C 99 0d h 10 second second watchdog 00 C 99 0e h blf1 blf2 prs pab tdf ksf wdf irqf control a 0f h te cs bme tpe tie kie wde wds control b 10 h extended ram address ram address lsb 00 C ff 11 h reserved 12 h reserved 13 h extended ram data ram data 00 C ff 14 h - 1f h reserved 0 = 0 and are read only. power- up default states these bits are set upon power - up: eosc = 0, e32k = 0, tie = 0, kie = 0, wde = 0, and wds = 0. note: unless otherwise specified, the state o f the control/rtc/sram bits in the ds1500 is not defined upon initial power application; the ds1500 should be properly configured/defined during initial configuration. using the clock alar m the alarm settings and control reside within registers 08h to 0bh (table 2). the tie bit and alarm mask bits am1 to am4 must be set as described below for the irq or pwr outputs to be activated for a matched alarm condition. the alarm functions as long as at least one supply is at a valid level. note that activating the pwr pin requires the use of v baux .
ds1500 y2k watchdog rtc with nonvolatile control 14 of 20 the alarm can be programmed to activate on a specific day of the month, day of the week, or repeat every day, hour, minute, or second. it can also be programmed to go off while the ds1500 is in the battery - backed state of operation to serve as a system wakeup. alarm mask bits am1 to am4 control the alarm mode. table 3 shows the possible settings. configurations not listed in the table default to the once -per - second mode to notify the user of an incorrect alarm setting. w hen the rtc register values match alarm register settings, the time -of - day/date alarm flag tdf bit is set to 1. once the tdf flag is set, the tie bit enables the alarm to activate the irq pin. the tpe bit enables the alarm flag to activate the pwr pin. the alarm functions on v cc , v bat , and v baux . table 3 . alarm mask bits dy/dt am4 am3 am2 am1 alarm rate x 1 1 1 1 once per second x 1 1 1 0 when seconds match x 1 1 0 0 when minutes and seconds match x 1 0 0 0 when hours, minutes, and seconds match 0 0 0 0 0 when date, hours, minutes, and seconds match 1 0 0 0 0 when day, hours, minutes, and seconds match control registers the controls and status information for the ds1500 features are maintained in the following register bits. month register (05h) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 eosc e32k bb32 10 month month eosc, oscillator start/stop bit (05h bit 7) this bit when set to logic 0 starts the oscillator. when this bit is set to logic 1, the oscillator is stoppe d. this bit is automatically set to logic 0 by the internal power - on reset when power is applied and v cc rises above the power - fail voltage. e32k, enable 32.768khz output (05h bit 6) this bit, when written to 0, enables the 32.768 khz oscillator frequency to be output on the sqw pin if the oscillator is running. this bit is automatically set to logic 0 by the internal power - on reset when power is applied and v cc rises above the power - fail voltage. bb32, battery backup 32khz enable bit (05h bit 5) when the bb32 bit is written to 1, it enables a 32khz signal to be output on the sqw pin while the part is in battery - backup mode, if voltage is applied to v baux. am1 to am4, alarm mask bits ( 08h bit 7; 09h bit 7; 0ah bit 7; 0bh bit 7) bit 7 of re gisters 08h to 0bh contains an alarm mask bit, am1 to am4. these bits, in conjunction with the tie described later, allow the irq output to be activated for a matched - alarm condition. the alarm can be programmed to activate on a specific day of the month, day of the week, or repeat every day, hour, minute, or second. table 3 shows the possible settings for am1 to am4 and the resulting alarm rates. configurations not listed in the table default to the once -per - second mode to notify the user of an incorrect a larm setting. dy/dt, day/date bit ( 0bh bit 6) the dy/dt bit controls whether the alarm value stored in bits 0 to 5 of 0bh reflects the day of the week or the date of the month. if dy/dt is written to a 0, the alarm is the result of a match with th e date of the month. if dy/dt is written to a 1, the alarm is the result of a match with the day of the week.
ds1500 y2k watchdog rtc with nonvolatile control 15 of 20 control a register (0eh) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 blf1 blf2 prs pab tdf ksf wdf irqf blf1, valid ram and time bit 1 (0e h bit 7); blf2, valid ram and time bit 2 (0eh bit 6) these status bits give the condition of any batteries attached to the v bat or v baux pins. t he ds1500 constantly monitors the battery voltage of the backup - battery sources (v bat and v baux ). the blf1 and b lf2 bits are set to 1 if the battery voltage on v bat and v baux is less than v blf , otherwise blf1 and blf2 bits are 0. blf1 reflects the condition of v bat with blf2 reflecting v baux . if either bit is read as 1, the voltage on the respective pin is inadequat e to maintain the ram memory or clock functions. these bits are read only. prs, reset select bit (0eh bit 5) when set to 0, the pwr pin is set high - z when the ds1500 goes into power - fail. when set to 1, the pwr pin remains active upon entering power - fail. pab, power active - bar control bit (0eh bit 4) when this bit is 0, the pwr pin is in the active - low state. when this bit is 1, the pwr pin is in the high - impedance state. the user can write this bit to 1 or 0. if either tdf and tpe = 1 or ksf = 1, the pab bit is cleared to 0. this bit can be read or written. tdf, time -of - day/date alarm flag (0eh bit 3) a 1 in the tdf bit indicates that the current time has matched the alarm time. if the tie bit is also 1, the irq pin goes low and a 1 appears in the irqf b it. this bit is cleared by reading the register or writing it to 0. ksf, kickstart flag (0eh bit 2) this bit is set to 1 when a kickstart condition occurs or when the user writes it to 1. if the kie bit is also 1, the irq pin goes low and a 1 appears in t he irqf bit. this bit is cleared by reading the register or writing it to 0. wdf, watchdog flag (0eh bit 1) if the processor does not access the ds1500 with a write within the period specified in addresses 0ch and 0dh , the wdf bit is set to 1. wdf is cleared by writing it to 0. irqf, interrupt request flag (0eh bit 0) the interrupt request flag (irqf) bit is set to 1 when one or more of the following are true: tdf = tie = 1 ksf = kie = 1 wdf = wde = 1 i.e., irqf = (tdf x tie) + (ksf x kie) + (wdf x wde) any time the irqf bit is 1, the irq pin is driven low. clearing irq and flags the time -of - day/date alarm flag (tdf), watchdog flag (wdf), kickstart flag (ksf) and interrupt request flag (irqf) are cleared by reading the flag register ( 0eh ). the address must be stable for a minimum of 15ns while cs and oe are active. after the address stable requirement has been met, either a change in address, a rising edge of oe , or a rising edge of cs causes the flags to be cleared. the irq pin goes inactive a fter the irqf flag is cleared. tdf and wdf can also be cleared by writing to 0.
ds1500 y2k watchdog rtc with nonvolatile control 16 of 20 control b register (0fh) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 te cs bme tpe tie kie wde wds te, transfer enable bit (0fh bit 7) when the te bit is 1, the update transfer functions normally by advancing the counts once per second. when the te bit is written to 0, any update transfer is inhibited and the program can initialize the time and calendar bytes without an update occurring in the midst of initializing. rea d cycles can be executed in a similar manner. te is a read/write bit that is not modified by internal functions of the ds1500. cs, crystal select bit (0fh bit 6) when cs is set to 0, the oscillator is configured for operation with a crystal that has a 6pf specified load capacitance. when cs = 1, the oscillator is configured for a 12.5pf crystal. bme, burst - mode enable bit (0fh bit 5) the burst - mode enable bit allows the extended user ram ad dress registers to automatically increment for consecutive reads and writes. when bme is set to 1, the automatic incrementing is enabled; when bme is set to 0, the automatic incrementing is disabled. tpe, time -of - day/date alarm power- enable bit (0fh bit 4) the wakeup feature is controlled through the tpe bit. when the tdf flag bit is set to 1, if tpe is 1, the pwr pin is driven active. therefore, setting tpe to 1 enables the wakeup feature. writing a 0 to tpe disables the wakeup feature. tie, time -of -day/ date alarm interrupt - enable bit (0fh bit 3) the tie bit allows the tdf flag to assert an interrupt. when the tdf flag bit is set to 1, if tie is 1, the irqf flag bit is set to 1. writing a 0 to the tie bit prevents the tdf flag from setting the irqf flag. kie, kickstart enable - interrupt bit (0fh bit 2) when v cci voltage is absent and kie is set to 1, the pwr pin is driven active low when a kickstart condition occurs (ks pulsed low), causing the ksf bit to be set to 1. when v cci is then applied, the irq pin is also driven low. if kie is set to 1 while system power is applied, both irq and pwr are driven low in response to ksf being set to 1. when kie is cleared to a 0, the ksf bit has no effect on the pwr or irq pins. wde, watchdog enable bit (0fh bit 1) wh en wde is set to 1, the watchdog function is enabled, and either the irq or rst pin is pulled active based on the state of the wds and wdf bits. this bit is automatically cleared to logic 0 to by the internal power - on reset when power is applied and v cc ri ses above the power - fail voltage. wds, watchdog steering bit (0fh bit 0) if wds is 0 when the watchdog flag bit wdf is set to 1, the irq pin is pulled low. if wds is 1 when wdf is set to 1 , the watchdog outputs a negative pulse on the rst output. the wde bit resets to 0 immediately after rst goes active. this bit is automatically cleared to logic 0 to by the internal power - on reset when power is applied and v cc rises above the power - fail voltage. clock oscillator con trol the clock oscillator can be stoppe d at any time. to increase the shelf life of a backup lithium - battery source, the oscillator can be turned off to minimize current drain from the battery. the eosc bit is used to control the state of the oscillator, and must be set to 0 for the oscillator to function. using the watchdog t imer the watchdog timer can be used to restart an out -of - control processor. the watchdog timer is user programmable in 10ms intervals ranging from 0.01 seconds to 99.99 seconds. the user programs the watchdog timer by writ ing the timeout value into the two bcd watchdog registers (address 0ch and 0dh). the watchdog reloads and restarts whenever the watchdog times out. if either watchdog register is nonzero, a timeout sets the wdf bit to 1,
ds1500 y2k watchdog rtc with nonvolatile control 17 of 20 regardless of the state of the watc hdog enable (wde) bit, to serve as an indication to the processor that a watchdog timeout has occurred. the watchdog timer operates in two modes, repetitive and single - shot. if wde is 1 and the watchdog steering bit (wds) is 0, the watchdog is in repetiti ve mode. when the watchdog times out, both wdf and irqf are set. irq goes active and irqf goes to 1. the watchdog timer is reloaded when the processor performs a write of the watchdog registers and the timeout period restarts. reading the control a registe r clears the irq flag. if wde and wds are 1, the watchdog is in single - shot mode. when the watchdog times out, rst goes active for a period of t rec . when rst goes inactive, wde resets to 0. writing a value of 00h to both watchdog registers disables the wa tchdog timer. the watchdog function is automatically disabled upon power - up by the power - on reset setting wde = 0 and wds = 0. the watchdog registers are not initialized at power - up and should be initialized by the user. note: the te bit must be used to d isable transfers when writing to the watchdog registers. the following summarizes the configurations in which the watchdog can be used: wde = 0 and wds = 0: wdf is set. wde = 0 and wds = 1: wdf is set. wde = 1 and wds = 0: wdf and irqf are set, and the i rq pin is pulled low. wde = 1 and wds = 1: wdf is set, the rst pin pulses low, and wde resets to 0. wakeup/kickstart the ds1500 incorporates a wakeup feature, which powers on at a predetermined date by activating the pwr output pin. in addition, the kicks tart feature allows the system to be powered up in response to a low - going transition on the ks pin, without operating voltage applied to the v cci pin. as a result, system power can be applied upon such events as key closure, or a modem - ring - detects signal . to use either the wakeup or the kickstart features, the ds1500 must have an auxiliary battery connected to the v baux pin, and the oscillator must be running. the wakeup feature is controlled through the time -of - day/date power - enable bit (tpe). setting t pe to 1 enables the wakeup feature. transfers (te) must be enabled for a wake up event to occur. writing tpe to 0 disables the wakeup feature. similarly, the kickstart feature is controlled through the kickstart interrupt - enable bit (kie). if the wakeup f eature is enabled, while the system is powered down (no v cci voltage), the clock/calendar monitors the current day or date for a match condition with day/date alarm register (0bh). with the day/date alarm register, the hours, minutes, and seconds alarm byt es in the clock/calendar register map (02h, 01h, and 00h) are also monitored. as a result, a wakeup occurs at the day or date and time specified by the day/date, hours, minutes, and seconds alarm register values. this additional alarm occurs regardless of the programming of the tie bit. when the match condition occurs, the pwr pin is automatically driven low. this output can turn on the main system power supply, which provides v cci voltage to the ds1500 as well as the other major components in the system. a lso, at this time, the time -of - day/date alarm flag is set, indicating that a wakeup condition has occurred. if v baux is present, while v cc is low, the ks input pin is monitored for a low - going transition of minimum pulse width t kspw . when such a transitio n is detected, the pwr line is pulled low, as it is for a wakeup condition. also at this time, ksf is set, indicating that a kickstart condition has occurred. the ks input pin is always enabled and must be held at a valid logic lev el. the timing associated with these functions is divided into five intervals, labeled 1 to 5 on the diagram. the occurrence of either a kickstart or wakeup condition causes the pwr pin to be driven low, as described above. during interval 1, if the supp ly voltage on the v cci pin rises above the greater of v bat or v pf before the power - on timeout period (t poto ) expires, then pwr remains at the active - low level. if v cci does not rise above the greater of v bat or v pf in this time, then the pwr output pin is turned off and returns to its high - impedance level. in this event, the irq pin also remains tri - stated. the interrupt flag bit (either tdf or ksf) associated with the attempted power - on sequence remains set until cleared by software during a subsequent sys tem power -on.
ds1500 y2k watchdog rtc with nonvolatile control 18 of 20 if v cci is applied within the timeout period, then the system power - on sequence continues, as shown in intervals 2 to 5 in the timing diagram. during interval 2, pwr remains active, and irq is driven to its active - low level, indicating that e ither tdf or ksf was set in initiating the power - on. in the diagram, ks is assumed to be pulled up to the v baux supply. also at this time, the pab bit is automatically cleared to 0 in response to a successful power - on. the pwr line remains active as long a s the pab remains cleared to 0. at the beginning of interval 3, the system processor has begun code execution and clears the interrupt condition of tdf and/or ksf by writing 0s to both of these control bits. as long as no other interrupt within the ds1500 is pending, the irq line is taken inactive once these bits are reset, and execution of the application software can proceed. during this time, the wakeup and kickstart functions can be used to generate status and interrupts. tdf is set in response to a da y/date, hours, minutes, and seconds match condition. ksf is set in response to a low - going transition on ks . if the associated interrupt - enable bit is set (tde and/or kie), then the irq line is driven low in response to enabled event. in addition, the othe r possible interrupt sources within the ds1500 can cause irq to be driven low. while system power is applied, the on - chip logic always attempts to drive the pwr pin active in response to the enabled kickstart or wakeup condition. this is true even if pwr w as previously inactive as the result of power being applied by some means other than wakeup or kickstart. the system can be powered down under software control by setting the pab bit to 1. this causes the open - drain pwr pin to be placed in a high - impedanc e state, as shown at the beginning of interval 4 in the timing diagram. as v cci voltage decays, the irq output pin is placed in a high - impedance state when v cci goes below v pf . if the system is to be again powered on in response to a wakeup or kickstart, t hen both the tdf and ksf flags should be cleared, and tpe and/or kie should be enabled prior to setting the pab bit. during interval 5, the system is fully powered down. battery backup of the clock calendar and nv ram is in effect and irq is tri - stated, a nd monitoring of wakeup and kickstart takes place. if prs = 1, pwr stays active; otherwise, if prs = 0, pwr is tri - stated. square - wave output the square - wave output is enabled and disabled through the e32k bit. if the square wave is enabled ( e32k = 0) and the oscillator is running, then a 32.768khz square wave is output on the sqw pin. if the battery - backup 32khz - enable bit (bb32) is enabled, and voltage is applied to v baux , then the 32.768khz square wave is output on the sqw pin in the absence of v cci . b attery monitor the ds1500 constantly monitors the battery voltage of the backup - battery sources (v bat and v baux ). the battery low flags blf1 and blf2 are set to 1 if the battery voltages on v bat and v baux are less than 2.5v (typical); otherwise, blf1 and b lf2 are 0. blf1 monitors v bat and blf2 monitors v baux . 256 x 8 extended ram the ds1500 provides 256 x 8 of on - chip sram, which is controlled as nonvolatile storage sustained from a lithium battery. on power - up, the ram is taken out of write- protect status by an internal signal. two on - chip latch registers control access to the sram. one register is used to hold the sram address; the other is used to hold read/write data. the sram address space is from 00h to ffh. the 8 - bit address of the ram location to b e accessed must be loaded into the extended ram address register located at 10h. data in the addressed location can be read by performing a read operation from location 13h, or written to by performing a write operation to location 13h. data in any address ed location can be read or written repeatedly with changing the address in location 10h. to read or write consecutive extended ram locations, a burst mode feature can be enabled to increment the extended ram address. to enable the burst mode feature, set the bme bit to 1. with burst mode enabled, write the extended ram starting address location to register 10h. then read or write the extended ram data from/to register 13h. the extended ram address locations are automatically incremented on the rising edge of oe, cs , we only when register 13h is being accessed ( figure 4 ) . the address pointer wraps around after the last address is accessed.
ds1500 y2k watchdog rtc with nonvolatile control 19 of 20 pin configuration typical operating ci rcuit package inform ation for the latest package outline information and land patterns (footprints) , go to www.maxim - ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 32 tsop z32+4 21-0274 90-0320 maxim ds1500 cpu v cc v cci irq rst gnd x2 x1 rpu crystal sqw v bat dq0 C dq7 rst v baux ks pwr ce a0 C a4 irq gnd sram we oe cei ceo ce v cco v cc v cc v cc top view maxim ds1500 tsop (8mm x 20mm)
ds1500 y2k watchdog rtc with nonvolatile control 20 of 20 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 ? 20 11 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision date description pages changed 11/11 updated the features , ordering information , absolute maximum ratings , and package information ; corrected the operating temperature range for the ec tables 1 ? 4

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